1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, more particularly to a method of forming a stacked dielectric layer on a semiconductor substrate having metal patterns.
2. Description of the Related Art
Low dielectric constant (low k) materials have been widely used in Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) chips where interconnected wiring capacitance must be minimized.
FIGS. 1 is a cross-section showing the steps of a low k dielectric layer on a semiconductor substrate according to the prior art.
As shown in FIG. 1, a silicon semiconductor substrate 10 is provided. Metal patterns 14, for example of copper, are then formed in an inter-metal-dielectric (IMD) layer 12 followed by the deposition of a sealing layer 16. The dielectric layer 18, having a thickness from 6000 angstroms to about 8000 angstroms is formed on the sealing layer 16 by chemical vapor deposition (CVD) or spin coating. An anti-reflection layer 20 is then deposited on the dielectric layer 18 followed by conventional photolithography. The low k dielectric materials include inorganic materials formed by CVD and organic materials such
However, inorganic materials have generally high hardness and relatively high dielectric constant, making them unable to meet requirements when interconnected wiring capacitance must be minimized.
On the other hand, organic materials have generally low hardness, and relatively low dielectric constant, resulting in outgassing during the subsequent annealing process. Moreover, the dielectric constant (k) of the dielectric layer is varied and unstable. Furthermore, one dielectric layer with insufficient hardness may result in cracking during the package assembly process.
In view of the above disadvantages, an object of the invention is to provide a method of forming a stacked dielectric layer on a semiconductor substrate having metal patterns, thereby eliminating outgassing and cracking.
A further object of the invention is to provide a method of forming a stacked dielectric layer on a semiconductor substrate having metal patterns. This method can meet requirements when interconnected wiring capacitance must be minimized.
Accordingly, the above objects are attained by providing a method of forming a stacked dielectric layer on a semiconductor substrate having metal patterns. A first dielectric layer, having a thickness of 1000 to 1500 angstroms, is formed on the semiconductor substrate. Next, a second dielectric layer, having a thickness of 300 to 500 angstroms, is formed on the first dielectric layer to generate a composite dielectric layer. The second dielectric layer has a dielectric constant (k) higher than that of the first dielectric layer, a hardness higher than that of the first dielectric layer, and a thickness less than that of the first dielectric layer. The steps of forming the first dielectric layer and the second dielectric layer can be repeated at least 2 to 3 times to form a stacked dielectric layer. As well, an anti-reflection layer consisting of silicon oxy-nitride is preferably formed to cover the stacked dielectric layer.
In one embodiment of the invention, the first dielectric layer can be an organic material layer having dielectric constant of 1.5 to 2.7, a hardness from 0.6 Gpa to 1.5 Gpa. Alternately, an inorganic material layer formed by chemical vapor deposition can be used to replace the organic material layer. Moreover, the second dielectric layer can be silicon oxide, silicon nitride, silicon oxy-nitride, silicon carbide, or carbon doped silicon oxide and has a dielectric constant of 3 to 5. Also, the second dielectric layer has a hardness of 3 Gpa to 7 Gpa. Furthermore, the first dielectric layer and second dielectric layer can be formed in the same chemical vapor deposition tool.
The method of may further comprise a step of etching the composite dielectric layer to form a dual damascene structure by conventional via-first technology.
The method may also comprise the adhesion between the first dielectric layer and the second dielectric layer being 70 Mpa to 90 Mpa.